Overview
PSEC6 represents a newly presented Application Specific Integrated Circuit (ASIC) designed and simulated for picosecond-level timing resolution applications. Fabricated using the TSMC 65nm process, this ASIC incorporates an 8-channel architecture and is specified to operate at a maximum sampling rate of 40 GSa/s. A key feature is its integrated 10.24 GHz Phase Locked Loop (PLL), identified as the first of its kind within the 65nm CMOS process.
Research Context
The development of PSEC6 addresses the requirement for picosecond-level timing resolution, which is critical for enhancing performance in several specific areas. These areas include improved coincidence matching, time-of-flight measurements, and secondary vertex reconstruction. The ASIC's design aims to fulfill these resolution requirements through its specified sampling capabilities.
Approach
The PSEC6 ASIC design leverages the TSMC 65nm process. The architecture comprises 8 channels capable of high-speed waveform sampling. Integral to its operation is a 10.24 GHz PLL. The design documentation includes descriptions of the sampling architecture, the specific signal paths within the chip, and the detailed PLL design. The presented information includes specifications, design methodologies, and simulation outcomes for the PSEC6 ASIC.
Findings
- The PSEC6 ASIC is designed with 8 channels, enabling multi-channel data acquisition.
- A maximum sampling rate of 40 GSa/s is specified for the device.
- The ASIC incorporates a buffer with a length of 204.8 nanoseconds.
- A 10.24 GHz Phase Locked Loop (PLL) is integrated, noted as the first of its kind in the 65nm CMOS process.
- The event readout rate for PSEC6 is stated as 32 kHz.
- Digitization of sampled data is performed by an off-chip Analog-to-Digital Converter (ADC).
- Simulations predict an analog input bandwidth of 4.0 GHz for the ASIC.
- During sampling operations, the predicted power consumption is 20 mW per channel.
- The 10.24 GHz PLL exhibits a predicted jitter of 550 fs RMS.
- The predicted power consumption for the 10.24 GHz PLL is 15.7 mW.
Why This Matters
The achievement of picosecond-level timing resolution through devices like PSEC6 directly supports advancements in fields dependent on precise temporal measurements. Specifically, this capability is a prerequisite for improving techniques such as coincidence matching, which is fundamental in many detection systems, and enhancing the accuracy of time-of-flight measurements. Furthermore, it aids in the precision required for secondary vertex reconstruction, a process vital in particle physics experiments for identifying short-lived particles.