Overview
This research details an industrial-scale Performance Verification (PV) methodology developed for the AmpereOne custom CPU core. The methodology has been applied across four generations of this core. Its primary focus is on the cycle-accurate correlation between the Register-Transfer Level (RTL) design and a trace-driven performance model. The authors demonstrate the methodology's application through case studies of specific microarchitectural units, specifically the Branch Prediction Unit and the L2 Prefetcher.
Research Context
The contemporary landscape of process technology indicates a deceleration in scaling advancements. This trend positions microarchitectural innovation as the principal catalyst for achieving performance improvements in processor design. In this context, pre-silicon Performance Verification (PV) assumes heightened importance, becoming a more critical aspect of the development process.
Approach
The core of the presented methodology involves the cycle-accurate correlation of the RTL design against a trace-driven performance model. This overarching strategy is augmented by several integrated components:
- Data-Driven Workload Curation: A systematic process for selecting and preparing workloads based on data analysis.
- High-Frequency Daily Regression System: An automated system that executes tests frequently (daily) to monitor performance and identify regressions.
- Unified Event-Stream Framework: A standardized system for capturing and analyzing events during the verification process.
The methodology employs a hierarchical strategy for verification. This involves:
- Isolation of Individual Units: Initial focus on isolating and correlating individual microarchitectural units.
- Full-Core Verification: Subsequent progression to comprehensive verification of the entire CPU core.
Case studies involving the Branch Prediction Unit and the L2 Prefetcher are used to illustrate this hierarchical approach.
Findings
The application of this disciplined and iterative PV process yielded several key observations:
- The methodology is instrumental in avoiding post-silicon bugs, which are typically costly to address after the silicon manufacturing stage.
- It aids in ensuring that complex processors are able to meet their predefined performance targets.
- The hierarchical verification strategy, beginning with isolated unit correlation and progressing to full-core checks, effectively identifies and addresses performance-related issues.
Why This Matters
This methodology is indispensable for preventing expensive post-silicon errors and ensuring that complex processors achieve their intended performance specifications. Its application contributes to the successful development and deployment of high-performance CPU cores like the AmpereOne, particularly as microarchitectural advancements drive performance gains in an era of slowing process technology scaling.
Potential Applications
The described methodology for Performance Verification offers a framework applicable to the microprocessor industry. The paper concludes with a forward-looking perspective on the future trajectory of PV within this sector.